The present invention relates to a layout verifying method and layout verifying apparatus of a semiconductor integrated circuit.
In recent years, according to the microstructural progress of a semiconductor integrated circuit pattern, it has been demanded to form a pattern with high accuracy. It is known that the dimensions of a pattern on a semiconductor wafer formed by optically transferring a mask pattern on the wafer fluctuate depending on the coarseness and minuteness and the periodicity of the pattern. This variation in pattern forming accuracy due to the dimensional difference between patterns causes the deterioration in performance of a semiconductor device, posing a problem. The deterioration in pattern dimension accuracy is principally ascribed to an EB proximity effect, an optical proximity effect, an etching loading effect and so on. There has conventional been carried out mask pattern verification by a layout verifying apparatus so as not to significantly deteriorate the pattern dimensions.
FIG. 21 shows the construction of a prior art layout verifying apparatus. In a figure data input section 1, a layout figure from a layout data storing section 7 is read. A vector converting section 2 converts the layout figure into a vector description. A verifying section 5 successively selects vectors, verifies a distance to adjacent vectors according to a rule described by a verifying command 8 and outputs verification results to a verification result file 9. A verification result display section 6 displays the verification results outputted to the verification result file 9. This prior art layout verifying apparatus is to verify whether or not a design rule specified by minimum dimensions is satisfied with respect to the width of a pattern itself or an interval to the adjacent pattern.
With regard to the influence of interdependence between patterns, the verification has been simply executed by verifying a pitch defined by the sum total of the width W of the pattern itself and the interval S to the adjacent pattern as shown in FIG. 22.
However, the microstructural progress has become unable to ignore the increasing influence of the width of the adjacent pattern, the interval to the adjacent pattern and the width of the pattern on the dimensional accuracy as shown in FIG. 23. In FIG. 23, the reference numeral 21 denotes a design pattern 21, while the reference numeral 20 denotes a finished pattern on the wafer. In order to verify a pattern including the interdependence of patterns, the prior art apparatus has executed the steps of firstly selecting and extracting a pattern to be subjected to pattern dependency by arbitrary verification and verifying the pattern dependency by means of the selected extracted pattern. For example, when verifying the wiring pitch, there has been executed the steps of firstly extracting a pattern having an arbitrary pattern width and verifying the interval between the pattern and its pattern adjacent, thereby verifying whether or not the pitch is the permissible pitch. Although the microstructural progress has produced the need for pattern verification with higher accuracy, the prior art method has practically been unable to efficiently execute the verification with high accuracy.
Accordingly, the present invention has an object to provide a layout verifying method and apparatus capable of efficiently verifying with high accuracy a layout figure including inter-pattern interdependent dimensional accuracy.
In order to achieve the above object, the present invention provides a layout verifying method for converting a layout figure on a semiconductor integrated circuit into vector data by means of vectors corresponding to the sides of the layout figure and verifying whether or not the layout figure conforms to a design rule on the basis of the vector data, the method comprising:
a reference vector selecting step for selecting a reference vector which serves as a verification reference by its direction among vectors corresponding to the sides;
a verification object vector selecting step for executing search in a specified direction from the reference vector among the vectors corresponding to the sides and selecting the object vector to be verified; and
a verifying step for verifying a distance between each reference vector and the object vector to be verified.
With this layout verifying method of the present invention, a layout figure, inclusive of the dimensional accuracy depending on the pattern shape, can be efficiently verified with high accuracy.
According to the layout verifying method of the present invention, it is preferable to make a new reference vector of an error vector outputted as an error in the verifying step,
select a new object vector to be verified in correspondence with the new reference vector among the vectors corresponding to the sides and execute verification by the distance between the new reference vector and the new object vector to be verified corresponding to the new reference vector and a distance obtained through the above verification.
With this configuration layout figures of different design rules to be verified by the width of the adjacent pattern.
According to the layout verifying method of the present invention, it is acceptable to select the object vector to be verified on the basis of the magnitude of an angle between the object vector to be verified and the reference vector in the verification object vector selecting step. With this configuration the layout figures of different design rules that differ depending on the direction can be verified.
Furthermore, according to the layout verifying method of the present invention, it is acceptable to select the object vector to be verified on the basis of its direction and the number of vectors located between the object vector to be verified and the reference vector in the verification object vector selecting step. With this configuration the layout figure of which the design rule differs depending on the separated pattern can be verified.
Moreover, according to the layout verifying method of the present invention, it is acceptable to decide the presence or absence of an object vector to be verified within a prescribed range from the reference vector on the basis of the detected distance and output the error vector when no object vector to be verified exists within the prescribed range from the reference vector in the verifying step. With this configuration the pattern located relatively far apart from the adjacent pattern can be easily detected.
The present invention also provides a layout verifying apparatus for converting a layout figure on a semiconductor integrated circuit into vector data by means of vectors corresponding to the sides of the layout figure and verifying whether or not the layout figure conforms to a design rule on the basis of the vector data, the apparatus comprising:
a reference vector selecting section for selecting a reference vector which serves as a verification reference by its direction among vectors corresponding to the sides;
a verification object vector selecting section for executing search in a specified direction from the reference vector among the vectors corresponding to the sides and selecting the object vector to be verified; and
a verifying section for verifying a distance between each reference vector and the object vector to be verified.
With this layout verifying apparatus of present invention, the layout figure, inclusive of the dimensional accuracy depending on the pattern shape, can be efficiently verified with high accuracy.
According to the layout verifying apparatus of the present invention, it is acceptable to select the object vector to be verified on the basis of the magnitude of an angle between the object vector to be verified and the reference vector in the verification object vector selecting section. In this case, for example, a vector of to be verified at an angle of 45 degrees and an object vector to be verified at an angle of xe2x88x9245 degrees, which are relative to the reference vector, are classified into an identical group. With this configuration, the layout figure of which the design rule differs depending on the direction can be verified.
Furthermore, according to the layout verifying apparatus of the present invention, it is acceptable to select the object vector to be verified on the basis of its direction and the number of vectors located between the object vector to be verified and the reference vector in the verification object vector selecting section. With this configuration, the layout figure having the design rule that depends on the separated pattern can be verified.
Moreover, according to the layout verifying apparatus of the present invention, it is acceptable to decide the presence or absence of an object vector to be verified within a prescribed range from the reference vector on the basis of the detected distance and output the error vector when no object vector to be verified exists within the prescribed range from the reference vector in the verifying section. With this configuration, the pattern located relatively far apart from the adjacent pattern can easily detected.